1. Technical Field
Embodiments of the present disclosure generally relate to electronic systems.
2. Related Art
As fabrication processes of semiconductor devices such as memory chips rapidly develop, storage capacities of the memory chips have increased and operation speeds of the memory chips have increased as well. However, in such a case, widths of signal lines and spaces between the signal lines may be reduced. Reducing the widths of the signal lines and spaces between the signal lines may cause noise between the electrical signals or interferences between the electrical signals. As a result, the memory chips may malfunction due to the noise or the interference between the electrical signals.
In the event that spaces between adjacent circuits or adjacent power lines (or signal lines) of the semiconductor devices are reduced, parasitic capacitance values between the adjacent circuits or the adjacent power lines (or the adjacent signal lines) may increase. This may cause distortion or delay of data signals transmitted from transmitters to receivers through the power lines (or the signal lines). Thus, the semiconductor devices may malfunction. Accordingly, many efforts have been concentrated on a process design or a circuit design of the semiconductor devices to prevent the semiconductor devices from malfunctioning due to the noise or interference between the electrical signals.